Many high-speed field programmable gate array (FPGA) integrated circuits contain dynamic phase alignment (DPA) circuits. Some DPA circuits produce several candidate clock signals, all of which have the same frequency (related to the frequency of an input data signal received from outside the FPGA), and each of which has a unique phase. For example, there may be eight candidate clock signals, the phases of which are equally spaced over one clock signal cycle.
Phase detector circuitry compares the phase of transitions in the input data signal to the phase of transitions in one of the candidate clock signals. Assuming the phase detector does not detect a perfect phase match, the phase detector circuitry keeps moving from one candidate clock signal to the next trying to find the candidate clock signal having the phase that will be best for use in timing the sampling of the input data signal.
DPA circuits have dead zones. During the initial calibration, a DPA circuit may be unable to select a clock signal phase in the center of the sampling window of the input data signal if the initial clock signal phase falls within the dead zone.
A delay circuit can be inserted into the data path of the input data signal to move the input data signal outside the dead zone of the DPA circuit. However, the delay of the delay circuit varies based on variations in the process of the FPGA, the supply voltage provided to the delay circuit, the temperature of the FPGA, and the frequency of the input data signal. Variations in the delay of the delay circuit may cause the clock signal phase selected by the DPA circuit to remain in the dead zone. Also, the delay circuit in the data path of the input data signal may negatively affect the performance of other circuitry in the FPGA that is responsive to the input data signal.